One objective in chip performance is to obtain the maximum performance or speed for the least amount of power. Typically, a clock is generated using a phased lock loop (PLL) and then distributed to various circuits on a chip. Not all circuits on a chip are driven by clocks at the same frequency. A significant improvement in system performance can be obtained by increasing the clock frequency that is input to certain circuits, such as the arithmetic logic unit (ALU). For example, while many circuits on a chip may require a clock frequency of 1.times., the ALU may require a clock frequency of 2.times..
In addition, synchronous circuits require an input clock signal having a fixed or constant period. One period of a clock can be measured, for example as the time period from rising edge to rising edge of the clock signal, or from falling edge to falling edge. However, generating a clock signal having a fixed period can be very difficult.
FIG. 1 illustrates a timing diagram for two clock signals. As illustrated in FIG. 1, a 2.times. clock signal 7 is generated based on a 1.times. clock signal 5. The 1.times. clock signal 5 has a clock period of 14 gate delays, with 7 gate delays for each phase. Therefore, the 1.times. clock signal 5 has a 50% duty cycle because both phases of the clock cycle are 7 gate delays in width. Two periods of 2.times. clock signal 7 are generated during one period of the 1.times. clock signal 5.
Two periods (period 1 and period 2) of the 2.times. clock signal 7 are illustrated in FIG. 1. For period 1 of the 2.times. clock signal 7, a rising edge 3 of the 2.times. clock signal 7 is generated two gate delays after the rising edge of the 1.times. clock signal 5. Period 1 ends (and period 2 begins) on a rising edge 4 of the 2.times. clock signal 7, which occurs three gate delays after the falling edge of the 1.times. clock signal 5. Period 2 of the 2.times. clock signal 7 ends on a rising edge 8 of the 2.times. clock signal 7, which occurs two gate delays after the rising edge of the 1.times. clock signal 5.
The 2.times. clock signal 7 does not have a constant period clock because of an odd/even gate delay problem. An even number of gate delays are typically required to generate a rising edge (e.g., rising edge 3) from a rising edge. Also, an odd number of gate delays are typically required to generate a rising edge (e.g., rising edge 4) from a falling edge. In the example illustrated in FIG. 1, the rising edge 3 of the 2.times. clock signal 7 is delayed by two gate delays from the rising edge of the 1.times. clock signal 5. However, the rising edge 4 of the 2.times. clock signal 7 is delayed by three gate delays from the falling edge of the 1.times. clock signal 5. As a result, period 1 of the 2.times. clock signal 7 is eight gate delays wide, and period 2 is six gate delays wide. Therefore, the period of 2.times. clock signal 7 is not constant, which is unacceptable for a clock signal for synchronous circuits.
In the past, chip manufacturers have attempted to obtain a fixed period clock by adjusting the gate delays for selected transistors. However, this technique is very difficult to successfully implement and adds significant complexity to the chip design and semiconductor processing.
In addition, many prior art clock circuits used complementary metal oxide semiconductor (CMOS) static networks to generate clock signals. However, CMOS networks employ both n-channel and p-channel transistors for each inversion. As a result, these clock circuits have a high input capacitance, resulting in a low capacitive gain and requiring large devices to generate sufficient current. Also, the complementary (n-channel and p-channel) transistors of a CMOS network are turned on together at the same time during switching, thereby requiring even additional current. It is desirable to have clock circuits having a higher capacitive gain and requiring less current than the CMOS static networks.
Therefore, there is a need for a clock circuit that more efficiently generates a 2.times. clock signal having a constant clock period while improving capacitive gain.